The present invention relates to a storage apparatus, a writing method and a reading method and, more particularly, to such apparatus and methods suitable for use in performing hierarchical coding for forming images in hierarchical order having different number of pixels.
In a hierarchical coding method, high-resolution image data is set as image data in a lowermost layer or a first layer, image data in a second layer is formed of a number of pixels smaller than the number of first-layer pixels, image data in a third layer is formed of a further smaller number of pixels, followed by formation of image data from a fourth layer to a predetermined uppermost layer. Image data in each layer may be displayed on a monitor having a resolution (a number of pixels) corresponding to the layer. Accordingly, a user can select image data (hierarchically coded image data) corresponding to the resolution of the user""s monitor to view corresponding images. As an example, an image corresponding to one layer can be used for enlargement of an image corresponding to one of the respective higher layers in such a manner that, when the image corresponding to the higher layer is displayed, it is replaced with the image corresponding to the lower layer by a user operation or the like.
In setting image data having a certain resolution as image data of the lowermost layer (first layer), successively forming image data of upper layers, and storing or transmitting the image data of all the layers, a storage capacity or transmission capacity for the image data of the upper layers is required in addition to that for storage or transmission or the like of the image data of the lowermost layer only. A hierarchical coding method has been proposed which prevents such increase in storage capacity or the like. This method will be herein below described with respect to a three-layer hierarchical coding situation in which the sum of the values of four pixels, i.e., 2xc3x972 column and row arrangement of four pixels, is set as a pixel (pixel value) of an upper layer.
In FIG. 16, the 4xc3x974 arrangement of pixels are the pixels of the lowermost-layer image. A sum of the four pixel values h00, h10, h01, and h11 of such 4xc3x974 arrangement is calculated and set as an upper left pixel m0 of a second layer which is a 2xc3x972 pixel arrangement. Similarly, a sum m1 of the four pixel values h20, h30, h21, and h31, a sum m2 of the four pixel values h02, h12, h03, and h13, and a sum m3 of the four pixel values h22, h32, h23, and h33 are calculated and set as an upper right pixel, a lower left pixel, and a lower right pixel, respectively, of the second layer. Further, a sum q0 of the four pixel values m0, m1, m2, and m3 of the 2xc3x972 pixels in the second layer is calculated and set as a pixel of a third-layer image, which is the uppermost layer in this situation.
If all of the pixels h00 to h33, m0 to m3, and q0 described above are stored in their respective original forms, an additional storage capacity or the like corresponding to the second-layer pixels m0 to m3 and third-layer pixel q0 is required, as mentioned above. As a result, the third-layer pixel q0 may be set at the position corresponding to the lower right pixel m3 in the second-layer, as shown in FIG. 16, wherein the second layer is formed of pixels m0 to m2 and q0. Further, the second-layer pixel m0 may be set at the position corresponding to the lower right pixel h1 in the first-layer, as shown in FIG. 16. (Recall that m0 may be obtained from h00, h10, h01, and h11 of the first layer.) Similarly, the other second-layer pixels m1, m2, and q0 may also be set in pixels h31, h13, and h33 of the first layer. Although pixel q0 is not obtained directly from the first-layer pixels h22, h32, h23, and h33, pixel q0 (instead of pixel m3) is set at the position corresponding to pixel h33 because it is set in the second layer in place of m3 which was obtained directly from the first-layer pixels h22, h32, h23, and h33.
Thus, in the above-described situation, a total of 4xc3x974 or sixteen pixels may be formed. Such number of pixels is the same as that of the lowermost layer. As such, an increase in storage capacity or the like can be prevented.
Decoding of the above-described pixel q0 (which replaced m3 and h33) and pixels m0 to m2 (which respectively replaced pixels h11, h31, and h13) can be performed as described below.
That is, the value of q0 is the sum of m0 to m3 (i.e., q0=m0+m1+m2+m3). Therefore, m3 can be obtained from the equation m3=q0xe2x88x92(m0+m1+m2). Also, m0 is the sum of h00, h10, h01, and h11 (i.e., m0=h00+h10+h01+h11). Therefore, h11 can be obtained from the equation h11=m0xe2x88x92(h00+h10+h01). Each of h31, h13, and h33 may be obtained in a similar manner. The pixel h33 is obtained upon obtaining m3, as described above.
In the above-described hierarchical coding, a delay circuit for performing line delay of lower-layer pixels (pixel values) is utilized as well as a versatile memory (for example, a static random access memory (SRAM) or a dynamic RAM (DRAM)) for storing results of such hierarchical coding. As an example, and with reference to FIG. 16, an operation may be performed relating to the equation m0=h00+h10+h01+h11 to obtain the second-layer pixel m0, which utilizes first-layer pixels h00, h10, h01, and h11 in two lines. Image data may be supplied to (or written into) a memory in a predetermined order, such as a line scanning order from left to right and from top to bottom with respect to an arrangement of pixels. Image data may also be read out from the memory in line scanning order with respect to the pixels. Therefore, to obtain the second-layer pixel m0, an operation is performed in which the line starting at h00 is delayed by one line and one pixel to await supply of h01 and h11 of the line starting at h01, m0 is calculated and then the line starting at h00 is thereafter written to the memory.
Thus, in the above-described coding technique, a delay circuit for performing line delay of image data in addition to a memory for storing results of hierarchical coding may be utilized, thereby increasing the size of the respective coding apparatus and hindering the processing speed thereof.
An object of the present invention is to provide a hierarchical coding technique which does not utilize a delay circuit as in the above-described hierarchical coding apparatus.
Another object of the present invention is to provide a hierarchical coding apparatus having a relatively small size and capable of high-speed processing.
In accordance with an aspect of the present invention, a storage apparatus is provided for storing a first image corresponding to a low layer and having a plurality of pixels and a second image corresponding to a high layer and having a plurality of pixels, in which a pixel of the second image is formed from N pixels of the first image, and in which the pixels of the first image are inputted one by one in a predetermined order. The apparatus comprises a low layer storage device for storing the first image corresponding to the low layer; a high layer storage device for storing the second image corresponding to the high layer; a controller for controlling read and write operations with respect to the low layer and high layer storage devices, in which the controller reading out the first image stored in the low layer storage device as a unit group of Nxe2x88x921 pixels; and a pixel generator for generating one pixel of the second image by using the N pixels of the first image which include the Nxe2x88x921 pixels of the first image read out from the low layer storage device and one input pixel of the first image.
In accordance with another aspect of the present invention, a storage apparatus is provided for storing a first image corresponding to a low layer and having a plurality of pixels and a second image corresponding to a high layer and having a plurality of pixels, in which a pixel of the second image is formed from N pixels of the first image, and in which the pixels of the first image are inputted one by one in a predetermined order. The apparatus comprises a low layer storage device for storing the first image corresponding to the low layer in which the low layer storage device stores only Nxe2x88x921 pixels and excludes a final input pixel of the N pixels of the first image used to form the one pixel of the second image and in which the final input pixel is inputted in the N pixels of the first image and is not stored in the low layer storage device, a high layer storage device for storing the second image corresponding to the high layer in which high layer storage device stores one pixel of the second image by using the N pixels of the first image which include the Nxe2x88x921 pixels of the first image read out from the low layer storage device and the final input pixel of the first image, a controller for controlling read and write operations with respect to the low layer and high layer storage devices in which the controller reads out the one pixel of the second image in the high layer storage and in which the controller reads out the first image stored in the low layer storage device as a unit group of Nxe2x88x921 pixels, and a pixel generator for generating the final input pixel of the first image by using the one pixel of the second image read out from the high layer storage device and the Nxe2x88x921 pixels of the first image read out from the low layer storage device.
Other objects, features and advantages according to the present invention will become apparent from the following detailed description of illustrated embodiments when read in conjunction with the accompanying drawings in which corresponding components are identified by the same reference numerals.